Generally, a Thin Film Transistor(hereinafter referred to as TFT) is used as not only a load resistor in the high density Static Random Access Memory (SRAM), but also a driving means for Liquid Crystal Display.
In SRAM with memory capacities of the mega-bit, the reduced cell size and lowered supply voltage make it lower the potential level of the cell node which stores the information data `1`, which results in the instability in operation of the cell as a severe problem.
One of the methods for solving such a problem is to adopt an access transistor having the large size ratio (WD/LD)/(WA/LA) like a driver transistor, thereby increasing the cell ratio.
However, the solution is not suitable for the high density SRAM in that the cell size must be reduced.
There is another solution that as a load resistor the polysilicon TFT is employed instead of the polysilicon resistor in order to have the characteristics of the high charging current and low leakage current.
However, a problem arises in that a ratio of on to off current is not high enough to apply the polysilicon TFT to SRAM with memory capacities of 16 Mb.
Recently, there is provided a Lightly Doped Offset TFT (LDO TFT) which can be well adopted in a high density SRAM, which is disclosed in detail in the article of H. Ohkubo et al., 16 Mbit SRAM Cell Technologies for 2.0V Operation, IEDM.Tech.Dig., pp 481-484, 1991.
FIG. 1 is a sectional view of the conventional LDO TFT having a bottom gate.
Referring to FIG. 1, the conventional LDO TFT includes a substrate 11, an insulating layer 12 formed over the substrate 11, a gate 13 formed around a central portion of the insulating layer 12, a gate insulating layer 14 formed over the insulating layer 12 and covering the exposed whole surface of the gate 13, a semiconductor layer 15 formed over the gate insulating layer 14, a lightly doped p type impurity region 19 in the semiconductor layer 15 and near one side of the gate 13, and a highly doped p type impurity region 22 in the semiconductor layer 15 except for the gate 13 and p type impurity region 19.
The conventional LDO TFT has a bottom gate formed underneath the semiconductor layer 15, the source region in the semiconductor layer 15 and near one side of the gate 13, the source region including a single heavy p type impurity region 22, and the drain region in the semiconductor layer 15 and near other side of the gate 13, the drain region including a heavy p type impurity region 19 and a heavy p type impurity region 22 adjacent to the heavy p type impurity region 19.
FIGS. 2A through 2C are sectional views explaining the processing steps of making LDO TFT having the bottom gate.
As shown in FIG. 2A, the substrate 11 has the insulating layer 12 such as oxide layer on which a layer of polysilicon is deposited. The polysilicon layer is then patterned to form a gate located in the central portion of the insulating layer 12.
Over the whole surface of the substrate is formed a High Temperature Oxide layer 14 as the gate insulating layer on which a polysilicon layer is then deposited to form a semiconductor layer 15 followed by the Si ion implant so as to improve the feature of the semiconductor layer 15.
Through Si ion implant, the polysilicon layer is converted into the amorphous silicon layer, but the converted layer is subjected to the thermal treatment at the temperature of 600.degree..+-.50.degree. C. to form a polysilicon layer again, wherein the annealing can be performed by either a laser or an long thermal treatment above 5 hours. Further, one may employ the amorphous silicon layer instead of the polysilicon layer as the semiconductor layer 15. And, the impurity ions 16 are implanted into the semiconductor layer 16 to adjust the threshold voltage VT.
FIG. 2B shows the step of forming a Lightly Doped Drain(LDD) region in a predetermined portion of the semiconductor layer 15, which is formed coating a photoresist film 17 on the semiconductor layer 15 and selectively exposing the surface of the semiconductor layer 15 corresponding to the one side portion of the gate through the photolithographic technique.
The p type impurity ion is implanted towards the exposed surface of the semiconductor layer 15 to form a lightly doped drain area 19 except for the masked area by the patterned photoresist film 17.
FIG. 2C explains the step of forming the off-set source/drain region.
Upon removal the photoresist pattern 17, another photoresist film 20 is coated on the semiconductor layer 15 and through the photolithography the photoresist film is then patterned to expose the surface of the semiconductor layer 15 except for the some portion of the drain region 19 adjacent to the gate and for the portion which corresponds to the top surface portion of the gate 13. The p type impurity ion 21 is implanted towards the exposed surface of the semiconductor layer 15 to form the heavily doped off-set source/drain area 22 except for the masked area by the patterned photoresist film 20.
In general, preferably an off and on current of the TFT has to be low and high as possible, to have a higher ratio of on to off current as a main factor for improving the TFT characteristics.
The conventional off-set TFT has the feature of the reduced off current, but an on current of the device becomes low, which makes a problem of the low on/off current ratio thereby.
In the LDO TFT described above, it is possible to raise the on current, but the off current is higher than that of the off-set TFT, as a result, a ratio of on to off current can not be improved.
While it is necessary to make the semiconductor layer thin in order to reduce the off current of the TFT, the semiconductor layer is made thinner, resulting in the increase in the sheet resistance of the source/drain lines, which leads to the increase in the power consumption amount.